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DATA SHEET
MOS INTEGRATED CIRCUIT
PD72862
IEEE1394 OHCI HOST CONTROLLER
The PD72862 is IEEE1394 OHCI-Link controller. The PD72862 complies with the P1394a draft 2.0 specifications and works up to 400 Mbps. It supports both of the Cardbus interface and the PCI bus interface.
FEATURES
* Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 * Compliant with protocol enhancement as defined in P1394a draft 2.0 * Modular 32-bit host interface compliant to PCI Specification release 2.1 * Supports PCI-Bus Power Management Interface Specification release 1.0 * Supports Cardbus * Equipped CIS register * Cycle Master and Isochronous Resource Manager capable * Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface * Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) * 32-bit CRC generation and checking for receive/transmit packets * 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported * Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY * Internal control and operational registers direct-mapped to PCI configuration space * 2-wire Serial EEPROMTM interface supported
ORDERING INFORMATION
Part number Package 100-pin plastic TQFP (Fine pitch) (14 x 14)
PD72862GC-9EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14265EJ2V0DS00 (2nd edition) Date Published December 1999 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
1999
PD72862
FirewardenTM ROADMAP
Firewarden Series PC Application
1 Chip OHCI+PHY PD72870A 1 Chip OHCI+PHY PD72870 800M/1.6G p1394.b Link PD7286x
OHCI Link PD72862
IEEE1394-1995 Core Development
OHCI Link PD72861 OHCI Link PD72860
Hotline Link
1997
1998
1999
2000
2001
2
Data Sheet S14265EJ2V0DS00
PD72862
BLOCK DIAGRAM
Serial ROM Interface PCI Bus / Cardbus Interface
PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap
PCI-DMA
IOREG
CSR (CIS)
PFCOMM
Byte Swap ATF Byte Swap ITF
PCICFG
ATDMA PAU GRSU
ITCF
Byte RF Swap
Link Layer Core
OPCIBUS_ARB
GRQU ITDMA IRDMA0IRDMA3 SFIDU
RCF IOREG
ATDMA ATF CIS CSR IOREG IRDMA ITCF ITDMA ITF OPCIBUS_ARB PAU PCICFG PCIS_CNT PFCOMM RCF RF SFIDU
: Asynchronous Transmit DMA : Asynchronous Transmit FIFO : CIS Register : Control and Status Registers : IO Registers : Isochronous Receive DMA : Isochronous Transmit Control FIFO : Isochronous Transmit DMA : Isochronous Transmit FIFO : OPCI Internal Bus Arbitration : Physical Response and Request Unit : PCI Configuration Registers : PHY Control Isochronous Control : Pre Fetch Command FIFO : Receive Control FIFO : Receive FIFO : Self-ID DMA
PHY/Link Interface
OPCI Internal Bus PCIS Bus (PCI Slave Bus) PCIS_CNT
Data Sheet S14265EJ2V0DS00
3
PD72862
PIN CONFIGURATION (Top View)
Though the current implementation of the PD72862 includes signal pins for debugging and testing purpose, the package remains a cost efficient 100-pin TQFP package. * 100-pin plastic TQFP (Fine pitch) (14 x 14)
CLKRUN 78 3.3V VDD IDSEL LINKON 77 PCI VDD
PRST
PCLK
CBE3
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
INTA
REQ
PME
GNT
VSS
VSS
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
3.3V VDD AD21 AD20 AD19 AD18 V SS AD17 AD16 CBE2 FRAME PCI VDD IRDY TRDY DEVSEL STOP PERR SERR PAR V SS CBE1 AD15 AD14 AD13 AD12 3.3V VDD
100
76
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
3.3V VDD LPS LREQ SCLK V SS CTL0 CTL1 DIRECT D0 D1 D2 D3 V SS D4 D5 D6 D7 NC GROM_EN GROM_SCL GROM_SDA CARD_ON NC NC 3.3V VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 NC
49 NC
CIS_ON IC(L)
IC(H)
AD11
AD10
IC(L)
AD4
AD3
AD2
AD1
AD9
AD8
AD7
AD6
AD5
AD0
VSS
VSS
VSS
4
Data Sheet S14265EJ2V0DS00
PCI VDD
PIN_EN
CBE0
VSS
50
PD72862
PIN NAME
AD0-AD31 CARD_ON CBE0-CBE3 CIS_ON CLKRUN CTL0, CTL1 DEVSEL DIRECT D0-D7 FRAME GNT GROM_EN GROM_SCL GROM_SDA IC (H) IC (L) IDSEL INTA IRDY LINKON LPS LREQ NC PAR PCLK PERR PIN_EN PME PRST REQ SCLK SERR STOP TRDY VDD VSS : PCI Multiplexed Address and Data : PCI/Card Select : Command/Byte Enables : CIS Register ON : PCICLK Running : PHY/Link Bi-directional Control : Device Select : Auxiliary PHY/Link Signal : PHY/Link Bi-directional Data : Cycle Frame : Bus_master Grant : Serial EEPROM Enable : Serial EEPROM Clock Output : Serial EEPROM Data Input / Output : Internally Connected (High Clamped) : Internally Connected (Low Clamped) : ID Select : Interrupt : Initiator Ready : Link-On Request : Link Power Status : PHY/Link Request : Non-Connection : Parity : PCI Clock : Parity Error : Pin Enable Input : PME Output : Reset : Bus_master Request : PHY Clock : System Error : PCI Stop : Target Ready : Supply Voltage : Ground
Data Sheet S14265EJ2V0DS00
5
PD72862
CONTENTS 1. PIN 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 FUNCTIONS ..................................................................................................................................... 8 PCI Bus Interface Signals: (52 pins) .............................................................................................. 8 PCI/Cardbus Select Signals: (2 pins) ............................................................................................. 9 PHY/Link Interface Signals: (15 pins) .......................................................................................... 10 Serial ROM Interface Signals: (3 pins) ......................................................................................... 10 Miscellaneous Signal: (1 pin) ....................................................................................................... 10 IC: (3 pins) ...................................................................................................................................... 10 NC: (5 pins)..................................................................................................................................... 10 VDD: (8 pins) .................................................................................................................................... 10 VSS: (11 pins) .................................................................................................................................. 10
2. REGISTER DESCRIPTIONS................................................................................................................. 11 2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 11
2.1.1 Offset_00 2.1.2 Offset_02 2.1.3 Offset_04 2.1.4 Offset_06 2.1.5 Offset_08 2.1.6 Offset_09 2.1.7 Offset_0C 2.1.8 Offset_0D 2.1.9 Offset_0E 2.1.11 Offset_10 2.1.12 Offset_2C 2.1.13 Offset_2E 2.1.14 Offset_30 2.1.15 Offset_34 2.1.16 Offset_3C 2.1.17 Offset_3D 2.1.18 Offset_3E 2.1.19 Offset_3F 2.1.20 Offset_40 2.1.21 Offset_60 2.1.22 Offset_62 2.1.23 Offset_64 2.2.1 Offset_14/18 2.2.2 Offset_28 2.2.3 Offset_80 VendorID Register .............................................................................................................12 DeviceID Register..............................................................................................................12 Command Register............................................................................................................12 Status Register ..................................................................................................................13 Revision ID Register ..........................................................................................................14 Class Code Register..........................................................................................................14 Cache Line Size Register..................................................................................................14 Latency Timer Register .....................................................................................................14 Header Type Register .......................................................................................................14 Base Address 0 Register .................................................................................................15 Subsystem Vendor ID Register.......................................................................................15 Subsystem ID Register....................................................................................................15 Expansion Rom Base Address Register..........................................................................15 Cap_Ptr Register .............................................................................................................15 Interrupt Line Register.....................................................................................................16 Interrupt Pin Register ......................................................................................................16 Min_Grant Register .........................................................................................................16 Max Lat Register .............................................................................................................16 PCI_OHCI_Control Register ............................................................................................16 Cap_ID & Next_Item_Ptr Register ...................................................................................17 Power Management Capabilities Register.......................................................................17 Power Management Control/Status Register...................................................................17 Base_Address_1/2 Register (CardBus Status Registers) ............................................19
2.1.10 Offset_0F BIST Register ...................................................................................................................14
2.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 18
Cardbus CIS Pointer..........................................................................................................20 CIS Area ............................................................................................................................20
3. SERIAL ROM INTERFACE.................................................................................................................. 21 3.1 Serial EEPROM Register ............................................................................................................... 21 3.2 Serial EEPROM Register Description .......................................................................................... 21 3.3 Load Control................................................................................................................................... 25 3.4 Programming Sequence Example................................................................................................ 25 6
Data Sheet S14265EJ2V0DS00
PD72862
4. ELECTRICAL SPECIFICATIONS ......................................................................................................... 27 5. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 30 6. PACKAGE DRAWING .......................................................................................................................... 31 7. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 32
Data Sheet S14265EJ2V0DS00
7
PD72862
1. PIN FUNCTIONS 1.1 PCI Bus Interface Signals: (52 pins)
(1/2)
Name PAR I/O I/O Pin No. 18 IOL
PCI/Cardbus
Volts(V) 5/3.3
Function Parity is even parity across AD0-AD31 and CBE0-CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0-AD31 is an output.
AD0-AD31
I/O
2-5, 7, 8, 21-24, 27-30, 33-36, 39-42, 86-91, 93, 94, 98, 99
PCI/Cardbus
5/3.3
PCI Multiplexed Address and Data
CBE0-CBE3
I
9, 20, 32, 95
-
5/3.3
Command/Byte Enables are multiplexed Bus Commands & Byte enables.
FRAME
I/O
10
PCI/Cardbus
5/3.3
Cycle Frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle.
5
TRDY I/O 13
PCI/Cardbus
If Cardbus mode (CARD_ON = 1), this pin is should be pulled up to VDD. 5/3.3 Target Ready indicates that the current data phase of the transaction is ready to be completed. IRDY I/O 12
PCI/Cardbus
5/3.3
Initiator Ready indicates that the current bus master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus. During a read, its assertion indicates that the initiator is ready to accept data from the currently-addressed target.
REQ
O
84
PCI/Cardbus
5/3.3
Bus_master Request indicates to the bus arbiter that this device wants to become a bus master.
GNT
I
83
-
5/3.3
Bus_master Grant indicates to this device that access to the bus has been granted.
IDSEL
I
96
-
5/3.3
ID Select when actively driven, indicates that the IUHC is chipselected for configuration read/write transaction during the phase of device initialization.
5
DEVSEL I/O 14
PCI/Cardbus
If Cardbus mode (CARD_ON = 1), this pin is should be pulled up to VDD. 5/3.3 Device Select when actively driven, indicates that the driving device has decoded its address as the target of the current access. STOP I/O 15
PCI/Cardbus
5/3.3
PCI Stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction.
8
Data Sheet S14265EJ2V0DS00
PD72862
(2/2)
Name PME I/O O Pin No. 79 IOL
PCI/Cardbus
Volts(V) 5/3.3
Function PME Output for power management enable.
5
Caution The PME pin is not an N-channel open drain structure pin. Therefore, when using S3, S4, S5 state in ACPI, a circuit that can separate between the power supply and the PME pin externally is needed.
ACPI: Advanced Configuration and Power Interface. Please refer to ACPI Specification. CLKRUN I/O 78
PCI/Cardbus
5/3.3
PCICLK Running as input, to determine the status of PCLK; as output, to request starting or speeding up clock.
INTA PERR
O I/O
80 16
PCI/Cardbus PCI/Cardbus
5/3.3 5/3.3
Interrupt the PCI interrupt request A. Parity Error is used for reporting data parity errors during all PCI transactions, except a Special Cycle. It is an output when AD0AD31 and PAR are both inputs. It is an input when AD0-AD31 and PAR are both outputs.
SERR
O
17
PCI/Cardbus
5/3.3
System Error is used for reporting address parity errors, data parity errors during the Special Cycle, or any other system error where the effect can be catastrophic. When reporting address parity errors, it is an output.
PRST PCLK
I I
81 82
-
5/3.3 5/3.3
Reset PCI reset PCI Clock 33 MHz system bus clock.
1.2 PCI/Cardbus Select Signals: (2 pins)
Name CARD_ON CIS_ON I/O I I Pin No. 54 45 IOL Volts(V) 3.3 3.3 Function PCI/Card Select (1:Cardbus, 0:PCI bus) CIS Register ON CARD_ON 0 0 1 CIS_ON 1 0 X CIS off on on PME PME CSTSCHG CSTSCHG
Data Sheet S14265EJ2V0DS00
9
PD72862
1.3 PHY/Link Interface Signals: (15 pins)
Name D0-D7 I/O I/O Pin No. 59-62, 64-67 CTL0,CTL1 LREQ LINKON LPS SCLK DIRECT I/O O I O I I 69, 70 73 77 74 72 68 9mA 9mA 9mA 3.3 3.3 3.3 3.3 3.3 3.3 PHY/Link Bi-directional Control (ISO-barrier supported) PHY/Link Request (ISO-barrier supported) Link-On Request (ISO-barrier supported) Link Power Status (ISO-barrier supported) PHY Clock 49.152 MHz (ISO-barrier supported) Auxiliary PHY/Link Signal is used to determine whether the interconnection between Link and PHY has isolation (`low': ISObarrier; `high': no ISO-barrier). IOL 9mA Volts(V) 3.3 Function PHY/Link Bi-directional Data (ISO-barrier supported)
1.4 Serial ROM Interface Signals: (3 pins)
Name GROM_SDA GROM_SCL GROM_EN I/O I/O O I Pin No. 55 56 57 IOL 6mA 6mA Volts(V) 3.3 3.3 3.3 Function Serial EEPROM Data Input / Output Serial EEPROM Clock Output Serial EEPROM Enable (`high': GUID Load enabled; `low': GUID Load disabled)
1.5 Miscellaneous Signal: (1 pin)
Name PIN_EN I/O I Pin No. 43 IOL Volts(V) 5/3.3 Function Pin Enable Input (High clamped)
1.6 IC: (3 pins)
Name IC(H) IC(L) I/O I I Pin No. 44 46, 47 IOL Volts(V) 3.3 3.3 Function Internally Connected (High clamped) Internally Connected (Low clamped)
1.7 NC: (5 pins)
Name NC I/O Pin No. 48, 49, 52, 53, 58 IOL Volts(V) Non- Connection (Open) Leave them unconnected. Function
1.8 VDD: (8 pins)
VDD (5 V PCI or 3.3 V PCI) for PCI I/Os: 11, 37, 92 VDD 3 V for digital core & PHY/Link I/Os: 1, 25, 51, 75, 97
1.9 VSS: (11 pins)
VSS : 6, 19, 26, 31, 38, 50, 63, 71, 76, 85, 100
10
Data Sheet S14265EJ2V0DS00
PD72862
2. REGISTER DESCRIPTIONS 2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )
31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Cache Line Size 08H 0CH 10H 14H 18H 1CH 20H 24H 28H Subsystem Vendor ID Expansion Rom Base Address Register 000000H 00000000H Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control 00000000H 00000000H 00000000H Diagnostic register0 Diagnostic register1 Diagnostic register2 Diagnostic register3 Power Management Capabilities Data PMCSR_BSE 00000000H 00000000H User Area (GENERAL_RegisterA) User Area (GENERAL_RegisterB) User Area (GENERAL_RegisterC) User Area (GENERAL_RegisterD) 00000000H Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H FCH
DeviceID Status Class Code BIST Header Type
VendorID Command
Base Address 0 (OHCI Registers) Base Address 1 Base Address 2 Base Address 3 Base Address 4 Base Address 5 CardBus CIS Pointer Subsystem ID
Power Management Control/Status
Data Sheet S14265EJ2V0DS00
11
PD72862
2.1.1 Offset_00 VendorID Register This register identifies the manufacturer of the PD72862. The ID is assigned by the PCI_SIG committee.
Bits 15-0 R/W R Constant value of 1033H. Description
2.1.2 Offset_02
DeviceID Register
This register identifies the type of the device for the PD72862. The ID is assigned by NEC Corporation.
Bits 15-0 R/W R Constant value of 0063H. Description
2.1.3 Offset_04
Command Register
The register provides control over the device's ability to generate and respond to PCI cycles.
Bits 0 1 R/W R R/W Description I/O enable Constant value of 0. The PD72862 does not respond to PCI I/O accesses. Memory enable Default value of 1. It defines if the PD72862 responds to PCI memory accesses. This bit should be set to one upon power-up reset. 0: The PD72862 does not respond to PCI memory cycles 1: The PD72862 responds to PCI memory cycles 2 R/W Master enable Default value of 1. It enables the PD72862 as bus-master on the PCI-bus. 0: The PD72862 cannot generate PCI accesses by being a bus-master 1: The PD72862 is capable of acting as a bus-master 3 R Special cycle monitor enable Constant value of 0. The special cycle monitor is always disabled. 4 R/W Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid Command generation. 0: Memory write must be used 1: The PD72862, when acts as PCI master, can generate the command 5 R VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is always disabled. 6 R/W Parity error response Default value of 0. It defines if the PD72862 responds to PERR. 0: Ignore parity error 1: Respond to parity error 7 8 R R/W Stepping enable Constant value of 0. Stepping is always disabled. System error enable Default value of 0. It defines if the PD72862 responds to SERR. 0: Disable system error checking 1: Enable system error checking 9 R Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only allowed to the same agent. 15-10 R Reserved Constant value of 000000.
12
Data Sheet S14265EJ2V0DS00
PD72862
2.1.4 Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72862. "Read" and "Write" are handled somewhat differently.
Bits 3-0 4 6,5 7 R/W R R R R Reserved Constant value of 0000. New capabilities Constant value of 1. It indicates the existence of the Capabilities List. Description
Reserved Constant value of 00. Fast back-to-back capable Constant value of 1. It indicates that the PD72862, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent.
8
R/W
Signaled parity error Default value of 0. It indicates the occurrence of any "Data Parity". 0: No parity detected (default) 1: Parity detected
10,9
R
DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL. 0: Fast (1 cycles) 1: Medium (2 cycles) 2: Slow (3 cycles) 3: undefined
11
R/W
Signaled target abort Default value of 0. This bit is set by a target device whenever it terminates a transaction with "Target Abort". 0: The PD72862 did not terminate a transaction with Target Abort 1: The PD72862 has terminated a transaction with Target Abort
12
R/W
Received target abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with a "Target Abort". 0: The PD72862 has not received a Target Abort 1: The PD72862 has received a Target Abort from a bus-master
13
R/W
Received master abort
Default value of 0. This bit is set by a master device whenever its
transaction is terminated with "Master Abort". The PD72862 asserts "Master Abort" when a transaction response exceeds the time allocated in the latency timer field. 0: Transaction was not terminated with a Master Abort 1: Transaction has been terminated with a Master Abort 14 R/W Signaled system error Default value of 0. It indicates that the assertion of SERR by the
PD72862.
0: System error was not signaled 1: System error was signaled 15 R/W Received parity error Default value of 0. It indicates the occurrence of any PERR. 0: No parity error was detected 1: Parity error was detected
Data Sheet S14265EJ2V0DS00
13
PD72862
2.1.5 Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72862.
Bits 7-0 R/W R Description Default value of 02H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions.
2.1.6 Offset_09
Class Code Register
This register identifies the class code, sub-class code, and programming interface of the PD72862.
Bits 7-0 15-8 23-16 R/W R R R Description Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller. Constant value of 00H. It specifies an "IEEE1394" type. Constant value of 0CH. It specifies a "Serial Bus Controller".
2.1.7 Offset_0C
Cache Line Size Register
This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words. The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0, i.e. cache disabled.
Bits 7-0 R/W R/W Default value of 00H. Description
2.1.8 Offset_0D
Latency Timer Register
This register defines the maximum amount of time that the PD72862 is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction.
Bits 7-0 R/W R/W Description Default value of 00H. It specifies the number of PCI-bus clocks that the PD72862 may hold the PCI bus as a bus-master.
2.1.9 Offset_0E
Bits 7-0
Header Type Register
R/W R Description Constant value of 00H. It specifies a single function device.
2.1.10 Offset_0F BIST Register
Bits 7-0 R/W R Description Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.
14
Data Sheet S14265EJ2V0DS00
PD72862
2.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the "Operation registers" (i.e. control, configuration, and status registers) of the PD72862, while the BIOS is expected to set this value during power-up reset.
Bits 11-0 31-12 R/W R R/W Description Constant value of 000H. These bits are "read-only". -
2.1.12 Offset_2C
Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC's PD72862 function. While the ID is assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial EEPROM after power-up reset. Access to this register through PCI-bus is prohibited.
Bits 15-0 R/W R Default value of 1033H. Description
2.1.13 Offset_2E
Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC's PD72862 function. While the ID is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after power-up reset. Access to this register through PCI-bus is prohibited.
Bits 15-0 R/W R Default value of 0063H. Description
2.1.14 Offset_30
Expansion Rom Base Address Register
This register is not supported by the current implementation of the PD72862.
Bits 31-0 R/W R Reserved Constant value of 0. Description
2.1.15 Offset_34
Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the PD72862, the NEC's implementation of the 1394 OpenHCI specification.
Bits 7-0 R/W R Description Constant value of 60H. The value represents an offset into the PD72862's PCI Configuration Space for the location of the first item in the New Capabilities Linked List.
Data Sheet S14265EJ2V0DS00
15
PD72862
2.1.16 Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the PD72862, the NEC's implementation of the 1394 OpenHCI specification.
Bits 7-0 R/W R/W Description Default value of 00H. It specifies which input of the host system interrupt controller the interrupt pin of the PD72862 is connected to.
2.1.17 Offset_3D
Interrupt Pin Register
This register provides the interrupt line routing information specific to the PD72862, the NEC's implementation of the 1394 OpenHCI specification.
Bits 7-0 R/W R Description Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
2.1.18 Offset_3E
Min_Grant Register
This register specifies how long of a burst period the PD72862 needs, assuming a clock rate of 33MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM upon power-up reset, and access to this register through PCI-bus is prohibited.
Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
2.1.19 Offset_3F
Max Lat Register
This register specifies how often the PD72862 needs to gain access to the PCI-bus, assuming a clock rate of 33MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM after hardware reset, and access to this register through PCI-bus is prohibited.
Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
2.1.20 Offset_40
PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this register. It is reserved for OpenHCI use only.
Bits 0 R/W R/W Description PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to the PCI Interface are byte swapped, thus a "PCI Global Swap". PCI addresses for expansion ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not required for motherboard implementations. 31-1 R Reserved Constant value of all 0.
16
Data Sheet S14265EJ2V0DS00
PD72862
2.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72862's Capability List.
Bits 7-0 R/W R Description Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI Power Management registers, while the ID value is assigned by the PCI SIG. 15-8 R Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link List.
2.1.22 Offset_62
Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the
PD72862.
Bits 2-0 R/W R Description version Constant value of 001. The power management registers are implemented as defined in revision 1.0 of PCI Bus Power Management Interface Specification. 3 4 5 8,6 9 R R R R R PME clock Constant value of 0. Auxiliary power source Constant value of 0. The alternative power source is not supported. DIS Constant value of 0. Reserved Constant value of 000. D1_support Constant value of 0. The PD72862 does not support the D1 Power Management state. 10 15-11 R R D2_support Constant value of 1. The PD72862 supports the D2 Power Management state. PME_support Constant value of 01100.
2.1.23 Offset_64
Power Management Control/Status Register
This is a 16-bit read-only register that provides control status information of the PD72862.
Bits 1,0 R/W R/W Description PowerState Default value is undefined. This field is used both to determine the current power state of the PD72862 and to set the PD72862 into a new power state. As D1 is not supported in the current implementation of the PD72862, writing of `01' will be ignored. 00: D0 (DMA contexts: ON, Link Layer: ON) 01: Reserved (D1 state not supported) 10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active) 11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active, Power can be removed) 7-2 8 R R/W Reserved Constant value of 000000. PME_En Default value of 0. This field is used to enable the specific power management features of the PD72862. 12-9 14,13 15 R R R/W Data_Select Constant value of 0000. Data_Scale Constant value of 00. PME_Status Default value is undefined. A write of `1' clears this bit, while a write of `0' is ignored.
Data Sheet S14265EJ2V0DS00
17
PD72862
2.2 CardBus Mode Configuration Register ( CARD_ON=High )
31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Cache Line Size 08H 0CH 10H 14H 18H 1CH 20H 24H 28H Subsystem Vendor ID Expansion Rom Base Address Register 000000H 00000000H Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control 00000000H 00000000H 00000000H Diagnostic register0 Diagnostic register1 Diagnostic register2 Diagnostic register3 Power Management Capabilities Data PMCSR_BSE 00000000H 00000000H User Area (GENERAL_RegisterA) User Area (GENERAL_RegisterB) User Area (GENERAL_RegisterC) User Area (GENERAL_RegisterD) CIS Area Note Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H FCH
DeviceID Status Class Code BIST Header Type
VendorID Command
Base Address 0 (OHCI Registers) Base Address 1 (CardBus Status Reg) Note Base Address 2 (CardBus Status Reg) Base Address 3 Base Address 4 Base Address 5 CardBus CIS Pointer Note Subsystem ID
Note
Power Management Control/Status
Note Different from PCI Bus Mode Configuration Register.
18
Data Sheet S14265EJ2V0DS00
PD72862
2.2.1 Offset_14/18
Bits 7-0 31-8
Base_Address_1/2 Register (CardBus Status Registers)
R/W R R/W Constant value of 00. Description
(1) Function Event Register (FER) ( Base Address 1 ( 2 )+ 0H )
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wakeup Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description
(2) Function Event Mask Register (FEMR) ( Base Address 1 ( 2 )+ 4H )
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 5 6 13-7 14 15 31-16 R/W R R R R/W R/W R General Wakeup Mask BAM. Read only as `0' PWM. Read only as `0' Reserved. Read only as `0' Wakeup Mask Interrupt Reserved. Read only as `0' Description
Data Sheet S14265EJ2V0DS00
19
PD72862
(3) Function Reset Status Register (FRSR) ( Base Address 1 ( 2 )+ 8H )
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wakeup Mask Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description
(4) Function Force Event Register (FFER) ( Base Address 1 ( 2 )+ CH )
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R/W R General Wakeup Mask No Use Interrupt Reserved. Read only as `0' Description
2.2.2 Offset_28
Cardbus CIS Pointer
This register specifies start memory address of the Cardbus CIS Area.
Bits 31-0 R/W R Starting Pointer of CIS Area. Constant value of 00000080H. Description
2.2.3 Offset_80
CIS Area
The PD72862 supports external Serial ROM(AT24C02 compatible) interface. CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON are HIGH.
CARD_ON 0 0 1 CIS_ON 1 0 X Bus PCI PCI Cardbus CIS OFF ON ON FUNCTION PME CSTSCHG CSTSCHG
20
Data Sheet S14265EJ2V0DS00
PD72862
3. SERIAL ROM INTERFACE
The PD72862 provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM.
3.1 Serial EEPROM Register
Register Address Base address + 0x930 Base address + 0x934 Base address + 0x938 Base address + 0x93C Base address + 0x940 Base address + 0x95C Base address + 0x960 Base address + 0x984 SUBID register LATVAL register W_GUIDHi register W_GUIDLo register Parameters Write register W_GENERAL register W_PHYS register W_CIS register Register Name R/W R/W R/W R/W R/W R/W R/W R/W R/W
Remark Base address : Base Address 0 in Configuration register
3.2 Serial EEPROM Register Description
(1) SUBID register (Base address + 0x930)
31 W_SUBSYSID 16 15 W_SUBVNDID 0
Field W_SUBSYSID
Bits 31-16
R/W R/W
Default value 0063H
Description Subsystem ID value. The value is loaded into Subsystem ID register in Configuration register (offset+2CH bit 31-16).
W_SUBVNDID
15-0
R/W
1033H
Subsystem Vendor ID value. The value is loaded into Subsystem Vendor ID register in Configuration register (Offset+2CH bit 15-0).
(2) LATVAL register (Base address + 0x934)
31 W_MAXLAT 24 23 W_MINGNT 16 15 -012 11 10 1 -04 3 0
W_MAX_REC
Field W_MAXLAT
Bits 31-24
R/W R/W
Default value 00H
Description Max Latency value. The value is loaded into Max Latency register in Configuration register (Offset+3CH bit 31-24).
W_MINGNT
23-16
R/W
00H
Min Grant value. The value is loaded into Min Grant register in Configuration register (Offset+3CH bit 23-16).
-
15-12 11 10-4
R/W
9H
Reserved. Write 0 to these bits. Reserved. Write 1 to this bit. Reserved. Write 0 to these bits. MAX__REC value. The value is loaded into the max_rec field of OHCI BusOption register in OHCI register (Offset+020H bit 15-12).
W_MAX_REC
3-0
Data Sheet S14265EJ2V0DS00
21
PD72862
(3) W_GUIDHi register (Base address + 0x938)
31 W_GUIDHi 0
Field W_GUIDHi
Bits 31-0
R/W R/W
Default value Undefined
Description GlobalUniqueIDHi value. The value is loaded into OHCI GlobalUniqueIDHi register in OHCI register (Offset+024H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5].
(4) W_GUIDLo register (Base address + 0x93C)
31 W_GUIDLo 0
Field W_GUIDLo
Bits 31-0
R/W R/W
Default value Undefined
Description GlobalUniqueIDLo value. The value is loaded into GlobalUniqueIDLo register in OHCI register (Offset+028H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5].
(5) Parameters Write register (Base address + 0x940)
31 -07 6 4 3 -01 0
PAR _W
PAGE_S
Field PAGE_S
Bits 31-7 6-4
R/W R/W
Default value 000 Reserved. Write 0 to these bits.
Description
Write register select page. The bit field returns zero when read. 000: Select SUBID register and LATVAL register. 001: Select W_GUIDHi register and W_GUIDLo register. 010: Select W_GENERAL register (W_GENERAL_0 and W_GENERAL_1). 011: Select W_GENERAL register (W_GENERAL_2 and W_GENERAL_3). 100: Select W_PHYS register (W_ programPhyEnable, W_aPhyEnhanceEnable). 101: Select W_CIS register (W_CIS_EVEN - W_CIS_ODD).
PAR_W
3-1 0
R/W
0
Reserved. Write 0 to these bits. Write control signal. The bit field returns zeros when read. 1: Write the value of select page defined PAGE_S. One write transaction is the units of 8 byte. 0: Ignored.
22
Data Sheet S14265EJ2V0DS00
PD72862
(6) W_GENERAL register (Base address + 0x950 - 0x95C)
31 W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C) 0
Field W_GENERAL_0 W_GENERAL_3
Bits 31-0
R/W R/W
Default value Undefined
Description User define value. The value is loaded into GENERAL_registerA - D in Configuration register (Offset+70H - 7BH).
(7) W_PHYS register (Base address + 0x960)
31 -010 9 8 7 -0W_aPhyEnhanceEnable W_programPhyEnable 3 2 -10
Field W_programPhyEnable
Bits 31-10 9
R/W R/W
Default value 1 Reserved. Write 0 to these bits.
Description
programPhyEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.7]. 1: P1394a enhancement is supported. 0. P1394a enhancement is not supported.
W_aPhyEnhanceEnable
8
R/W
0
aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)).
-
7-3 2-0
-
-
Reserved. Write 0 to these bits. Reserved. Write 1 to these bits.
(8) W_CIS register (Base address + 0x980 - 0x984)
31 W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984) 0
Field W_CIS_EVEN W_CIS_ODD
Bits 31-0
R/W R/W
Default value Undefined
Description CIS Area value. The value is loaded into CIS Area in Configuration register (Offset+80H - FCH).
Data Sheet S14265EJ2V0DS00
23
PD72862
Table 3-1. Serial EEPROM Memory Map
Byte address 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 : : 1C 1D 1E 1F 20 21 22 23 : : 28 29 2A 2B : : A4 A5 A6 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 W_SUBSYSID(31 : 24) W_SUBSYSID(23 : 16) W_SUBVNDID(15 : 8) W_SUBVNDID( 7 : 0) W_MAXLAT(31 : 24) W_MINGNT(23 : 16) 0 0 W_GUIDHi(31 : 24) W_GUIDHi(23 : 16) W_GUIDHi(15 : 8) W_GUIDHi( 7 : 0) W_GUIDLo(31 : 24) W_GUIDLo(23 : 16) W_GUIDLo(15 : 8) W_GUIDLo( 7 : 0) W_GENERAL_0(31 : 24) W_GENERAL_0(23 : 16) W_GENERAL_0(15 : 8) W_GENERAL_0( 7 : 0) : : W_GENERAL_3(31 : 24) W_GENERAL_3(23 : 16) W_GENERAL_3(15 : 8) W_GENERAL_3( 7 : 0) 0 0 0 0 : : W_CIS_0(31 : 24) W_CIS_0(23 : 16) W_CIS_0(15 : 8) W_CIS_0( 7 : 0) : : W_CIS_31(31 : 24) W_CIS_31(23 : 16) W_CIS_31(15 : 8) W_CIS_31( 7 : 0) 0 0 0 0 0 0 0 1 0 0 WPE 1 0 0 WPEE 1 1 0 0 0
W_MAX_REC( 3 : 0)
WPE: W_programPhyEnable, WPEE: W_aPhyEnhanceEnable
24
Data Sheet S14265EJ2V0DS00
PD72862
3.3 Load Control
GROM_EN CARD_ON 0 1 X 0 CIS_ON X 1 No loading. W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable are loaded. 1 1 0 1 0 X All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable, W_CIS_EVEN - W_CIS_ODD) are loaded. Description
3.4 Programming Sequence Example
The example of programming sequence to the serial EEPROM is shown below. (1) Write SUBID register. Note1 (2) Write LATVAL register. Note1 (3) Write PAGE_S = 000 and PAR_W = 1 on Parameters Write register. Note1 (4) Wait over 13 ms for serial EEPROM access time. Note1 (5) Write W_GUIDHi register. Note2 (6) Write W_GUIDLo register. Note2 (7) Write PAGE_S = 001 and PAR_W = 1 on Parameters Write register. Note2 (8) Wait over 13 ms for serial EEPROM access time. Note2 (9) Write W_GENERAL register (W_GENERAL_0, W_GENERAL_1). Note3 (10) Write PAGE_S = 010 and PAR_W = 1 on Parameters Write register. Note3 (11) Wait over 13 ms for serial EEPROM access time. Note3 (12) Write W_GENERAL register (W_GENERAL_2, W_GENERAL_3). Note4 (13) Write PAGE_S = 011 and PAR_W = 1 on Parameters Write register. Note4 (14) Wait over 13 ms for serial EEPROM access time. Note4 (15) Write W_PHYS register (W_programPhyEnable, W_aPhyEnhanceEnable). Note5 (16) Write PAGE_S = 100 and PAR_W = 1 on Parameters Write register. Note5 (17) Wait over 13 ms for serial EEPROM access time. Note5 (18) Write W_CIS register (W_CIS_EVEN, W_CIS_ODD). Note6 (19) Write PAGE_S = 101 and PAR_W = 1 on Parameters Write register. Note6 (20) Wait over 13 ms for serial EEPROM access time. Note6 (21) Repeat (18)-(20) 15 times. (22) Complete to write parameters into Serial EEPROM. (23) Parameters are loaded from serial EEPROM after PCI reset. Notes 1. If none of W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC in serial EEPROM are changed, (1)-(4) transactions don't need. 2. If none of W_GUIDHi, W_GUIDLo in serial EEPROM are changed, (5)-(8) transactions don't need. 3. If none of W_GENERAL_0, W_GENERAL_1 in serial EEPROM are changed, (9)-(11) transactions don't need. 4. If none of W_GENERAL_2, W_GENERAL_3 in serial EEPROM are changed, (12)-(14) transactions don't need.
Data Sheet S14265EJ2V0DS00
25
PD72862
Notes 5. If none of W_programPhyEnable, W_aPhyEnhanceEnable in serial EEPROM are changed, (15)-(17) transactions don't need. 6. If none of W_CIS_0 - W_CIS_31 in serial EEPROM are changed, (18)-(21) transactions don't need.
26
Data Sheet S14265EJ2V0DS00
PD72862
4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Symbol VDD VI LVTTL @ (VI < 0.5 V + VDD) PCI @ (VI < 3.0 V + VDD) Output voltage VO LVTTL @ (VO < 0.5 V + VDD) PCI @ (VO < 3.0 V + VDD) Operating ambient temperature Storage temperature TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +6.6 0 to +70 -65 to +150 Unit V V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Ranges
Parameter Power supply voltage Symbol VDD Condition Used to clamp reflection on PCI bus. Rating 4.5 to 5.5 3.0 to 3.6 Operating ambient temperature TA 0 to +70 Unit V V C
Data Sheet S14265EJ2V0DS00
27
PD72862
DC Characteristics (VDD = 3.3 V 0.3 V, VSS = 0 V, TA= 0C to +70C)
Parameter High-level input voltage Low-level input voltage High-level output current Symbol VIH VIL IOH VOH
Pin No.48,49,52,53,58
Condition
MIN. 2.0 -0.5 -3 -6 -9 3 6 9
TYP.
MAX. VDD+0.5 +0.8
Unit V V mA mA mA mA mA mA
=2.4 V Pin No.55,56
Pin No.74
Low-level output current
IOL
VOL
Pin No.48,49,52,53,58
=0.4 V Pin No.55,56
Pin No.74
5 5
Input leakage current Supply current
IL IDD
VIN = VDD or GND VDD = 3.3 V D0 (Power State: 00) LPS = H 145
10.0
A
mA
PCI interface High-level input voltage Low-level input voltage High-level output current Low-level output current VIH VIL IOH IOL IL VOH = 2.4 V VOL = 0.4 V VIN = VDD or GND 2.0 -0.5 -2 9 10.0 5.5 +0.8 V V mA mA
5
Input leakage current PHY/Link interface Positive trigger voltage Negative trigger voltage High-level output current Low-level output current
A
VP VN IOH IOL VOH = 2.4 V VOL = 0.4 V
1.7 0.2 -9 9
3.1 1.6
V V mA mA
Remarks 1. Digital core runs at 3.3 V. 2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. 4. 5 V are used only for 5 V-PCI clamping diode.
3.3 V
5.0 V
Protection Circuit
I/O Buffer
28
Data Sheet S14265EJ2V0DS00
PD72862
AC Characteristics
PCI Interface See PCI local bus specification Revision 2.1. PHY/Link Interface
Parameter D,CTL setup time to SCLK rise D,CTL hold time to SCLK rise SCLK rise to D,CTL,LREQ out SCLK cycle time Symbol tDCSKS tDCSKH tD tSCLK CL = 10 pF Condition MIN. 6 0 1 20.345 10 TYP. MAX. Unit ns ns ns ns
PHY/Link Interface Timing
tSCLK SCLK tD CTL0,CTL1 tD D0-D7 tD tD tD tD
tDCSKS CTL0,CTL1 tDCSKS D0-D7
tDCSKH
tDCSKH
Serial ROM Interface See AT24C01A/02/04/08/16 Spec. Sheet.
Data Sheet S14265EJ2V0DS00
29
PD72862
5. APPLICATION CIRCUIT EXAMPLE
0.1F
0.1F 0.1F 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 LINKON 100 76 VSS
PME CLKRUN
3.3V VDD IDSEL
PCI VDD
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ
GNT
VSS
PRST
CBE3
PCLK
V power 3.3 V 3.3V V D D LPS LREQ SCLK V SS CTL0 CTL1 DIRECT D0 D1 D2 D3 V SS D4 D5 D6 D7 NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0.1F
1 2 3 4 0.1F 5 6 7 8 9
3.3V V D D AD21 AD20 AD19 AD18 V SS AD17 AD16 CBE2
10 F R A M E 11 PCI V D D 12 IRDY 13 T R D Y 14 D E V S E L 15 S T O P 16 P E R R 17 S E R R 18 P A R 19 V S S 20 C B E 1 21 A D 1 5 0.1F 22 A D 1 4 23 A D 1 3 24 A D 1 2 25 3.3V V D D 45 CIS_ON 46 IC(L) 42 AD0 43 PIN_EN 36 AD4 37 PCI VDD 32 CBE0 33 AD7 26 VSS 27 AD11 28 AD10 29 AD9 44 IC(H) 47 IC(L) 48 NC 49 NC 30 AD8 31 VSS 34 AD6 35 AD5 38 VSS 39 AD3 40 AD2 41 AD1
INTA
VSS
GROM_EN GROM_SCL GROM_SDA CARD_ON NC NC 3.3V V D D
50 VSS
0.1F
0.1F
V p o w e r 5 V /(3.3 V) 0.1F 33F
0.1F 33F
30
Data Sheet S14265EJ2V0DS00
PD72862
6. PACKAGE DRAWING
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D Q R
100 1
26 25
F G H P I
M
J
K
N
S
L M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. S100GC-50-9EU-2
Data Sheet S14265EJ2V0DS00
31
PD72862
5 7. RECOMMENDED SOLDERING CONDITIONS
The PD72850A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 7-1. Surface Mounting Type Soldering Conditions
PD72862GC-9EU : 100-pin plastic TQFP (Fine pitch) (14 x 14)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher). Count: three times or less Exposure limit: 3 daysNote (after that prebake at 125C for 10 hours) VPS Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher). Count: three times or less Exposure limit: 3 daysNote (after that prebake at 125C for 10 hours) Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) -- VP15-103-3 Soldering Conditions Recommended Condition Symbol IR35-103-3
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
32
Data Sheet S14265EJ2V0DS00
PD72862
[MEMO]
Data Sheet S14265EJ2V0DS00
33
PD72862
[MEMO]
34
Data Sheet S14265EJ2V0DS00
PD72862
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14265EJ2V0DS00
35
PD72862
EEPROM and Firewarden are trademarks of NEC Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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